A semiconductor charge transfer device (CTD) is a form of shift register or delay line device, in which an input data stream sequence of signal input charge packets is sequentially delayed and shifted through a succession of localized semiconductor charge transfer stages in a semiconductor medium. Each such transfer stage includes an integral number of charge storage sites to which a timed clock pulse sequence of voltage pulses is applied. There are as many storage sites per transfer stage as there are phases in the clock pulses. The desired sequential charge shift and storage operations through the CTD are obtained by means of a timed clock sequence of signal charge transfers from site to site, which results in response to the correspondingly timed clock sequence of voltages applied to the storage sites.
One particularly useful form of a semiconductor CTD is the "C4D", the Conductively Connected Charge Coupled Device, as described for example in an article by R. H. Krambeck (inventor herein) et al., entitled "Conductively Connected Charge-Coupled Device", published in IEEE Transactions on Electron Devices, Vol. ED-21, No. 1 (Jan. 1974), pp. 70-72; and in an article by C. N. Berglund et al., entitled "A Fundamental Comparison of Incomplete Charge Transfer in Charge Transfer Devices", published in Bell System Technical Journal, Vol. 52, No. 2 (Feb. 1973), pp. 147-182, at pp. 164-166. Briefly, such a device is driven by a two-phase clock pulse voltage source, and the device contains storage sites each of which has a p-n junction barrier located at the surface of the semiconductor underneath, and in registry with, the extremity of each driving electrode on the charge packet input side thereof. The two-phase clock voltage source contains two terminals, one for supplying clock voltage pulses during a sequence of time periods alternating with that of the other terminal.
One particular application of charge transfer devices is the design of such devices as circulating memories, in the form of a CTD in which a memory stream of data can circulate, in which the circulating stream of bits of data (information) can be modified ("updated") at will. Typically, this modification of the circulating sequence of bits of information is achieved by means of control circuitry located between an output and an input terminal of the circulating memory charge transfer device. This control circuitry typically contains at least one network ("write-enable") for enabling fresh data to be written into the circulating data as each datum reaches the control circuitry from an output terminal of the charge transfer device. In addition, the control circuitry also contains another input terminal to receive the desired sequence of new information to be written into the circulating memory during those periods of time in which the "write-enable" terminal(s) is activated by an external "write-enable" signal.
Control circuits for updating the information in a circulating semiconductor CTD memory suffer from the generation of spurious (error) signals which incorrectly rewrite data into the circulating memory. It has been thought that these error signals could be avoided by means of a single electrical charge drainoff means ("sink") connected to the output terminal of the charge transfer device. However, it has been found that even with the use of such charge drainoff means, the control circuitry nonetheless suffers from the production of spurious rewrite of data signals into the circulating memory.